Semiconductor packaging News

CITC and HAN course taps into increasing chip packaging complexity

July 17, 2020 – CITC and HAN University of Applied Sciences launch a Semiconductors Packaging Univerisity program. The program taps into the increasing chip packaging complexity. Bits&Chips’ Paul Greven talked to Joop Bruines, education consultant at CITC.

Need to cooperate

IC packaging has become increasingly complex and integral to the success of the overall semiconductor design process. Therefore, front-end engineers need to cooperate ever more closely with their back-end colleagues. Catering to this growing demand in the semiconductor industry, Chip Integration Technology Center (CITC), together with the HAN University of Applied Sciences, launch course in semiconductor packaging.

Completing the 5 month, fully certified Semiconductor Packaging University program will make graduates more effective at dealing with the increasingly complex interplay between the front and back-end technology that ultimately determines the performance of a semiconductor product.

Improving the interface between front-end and back-end

“It is important to semiconductor companies and their suppliers that their engineers, even if they are not directly involved with packaging and integration, are familiar with the issues and constraints associated with these technologies,” explains Joop Bruines. Bruines is involved in setting up the course at CITC and currently oversees the program at the HAN. “Front-end and back-end engineering aren’t exactly separate worlds these days, but the interface between them can definitely be improved. That is exactly what this course intends to achieve from the packaging perspective.”

Read the full article

Interested in joining this course that starts in September 2020? Please contact us  have a look at the HAN website.

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