article chip packaging course News

CITC and HAN course taps into increasing chip packaging complexity

BITS&CHIPS| Paul van Gerven | July 17 2020

As IC packaging becomes increasingly complex and integral to the success of the overall semiconductor design process, front-end engineers need to cooperate ever more closely with their back-end colleagues. CITC and the HAN University of Applied Sciences set up a packaging course to help them out.

Catering to growing demand in the semiconductor industry, Chip Integration Technology Center (CITC), together with the HAN University of Applied Sciences (HAN), is launching a course in semiconductor packaging. Completing the 5 month, fully certified Semiconductor Packaging University program will make graduates more effective at dealing with the increasingly complex interplay between the front and back-end technology that ultimately determines the performance of a semiconductor product.

“It is important to semiconductor companies and their suppliers that their engineers, even if they are not directly involved with packaging and integration, are familiar with the issues and constraints associated with these technologies,” explains Joop Bruines, who is involved in setting up the course at CITC and currently oversees the program at the HAN. “Front and back-end engineering aren’t exactly separate worlds these days, but the interface between them can definitely be improved. That is exactly what this course intends to achieve from the packaging perspective.”

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Interested in joining this course that starts in September 2020? Please contact us and let us know or have a look at the HAN website.